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TH50VPN5640EBSB
TENTATIVE TOSHIBA MULTI-CHIP INTEGRATED CIRCUIT SILICON GATE CMOS
PSEUDO SRAM AND NAND E2PROM MEMORY MIXED MULTI-CHIP PACKAGE DESCRIPTION
The TH50VPN5640EBSB is a mixed multi-chip package containing a 32-Mbit(33,554,432)bit pseudo static RAM and a 64-Mbit(69,206,016)bit NAND E2PROM organized as 528bytes x 16pages x 1024blocks. The power supply for the TH50VPN5640EBSB can range from 2.7 V to 3.1 V The TH50VPN5640EBSB is available in a 69-pin BGA package making it suitable for a variety of applications.
FEATURES
* * * Power supply voltage VCCs = 2.7 V~3.1 V VCCn = 2.7 V~3.1 V Pseudo SRAM page read operation mode Page read operation by 4 words Current consumption Operating: 30 mA maximum(CMOS level) Standby: 70 A maximum(Pseudo SRAM CMOS level) Standby: 100 A maximum(NAND E2PROM) NAND E2PROM Organization Memory cell allay 528 x 16K x 8 Register 528 x 8 Page size 528 bytes Block size (8K + 256) bytes
*
NAND E2PROM memory modes Read, Reset, Auto Page Program Auto Block Erase, Status Read NAND E2PROM Mode control Serial input/output Command control Program/Erase Cycles 2.5E5 ECC) cycle (with
*
* *
*
Package P-FBGA69-1209-0.80A3:0.31 g (typ.)
PIN ASSIGNMENT (TOP VIEW)
1 2 3 4 5 6 7 8 9 10
PIN NAMES
A0~A20 A0 , A1 DQ0~DQ15 Address Inputs Page Address Inputs for Pseudo SRAM Data Inputs/Outputs Chip Enable Input for NAND E PROM Output Enable Input for Pseudo SRAM Read enable Input for NAND E PROM Write Enable Input for Pseudo SRAM Write Enable Input for NAND E PROM Data Byte Control Input for Pseudo SRAM Ready/Busy Output Write Protect/Program Acceleration Input
2 2 2
A B C D E F G H J K L M
NC NC NC A3 A2 NC NC A1 A0 WP#n CE1S A7 A6 A5 A4 VSS OE /RE#n DQ0 DQ8 NC NC
NC NC
CE1S , CE2S Chip Enable Inputs for Pseudo SRAM CE#n OE / RE#n
LB
UB A18 A17 DQ1 DQ9
CLE CE#n ALE
WE /WE#n
CE2S A20
A8 A19 A9 A10 DQ6
A11 A12 A13 A14 NC A15 NC VCCn A16 NC NC
WE /WE#n LB , UB RY/BY
WP#n CLE ALE VCCs VCCn, Vccqn NC NC VSS NC
DQ3
DQ4 VCCs NC
DQ13 DQ15 RY/BY DQ12 DQ7 DQ5 DQ14 VSS
DQ10 VCCqn DQ2 DQ11
Command Latch Enable Address Latch Enable
Power Supply for Pseudo SRAM Power Supply for Ground Not Connected NAND E PROM
2
000707EBA2
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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BLOCK DIAGRAM
VCCn VCCqn CE#n CLE ALE WE#n RE#n WP#n
VSS
64 Mbits 2 NAND E PROM
DQ0~DQ7
RY/BY DQ0~DQ15 VCCs A0~A20 VSS
WE OE CE1S CE2S UB LB
32 Mbits PSEUDO SRAM
DQ0~DQ15
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MODE SELECTION
OPERATION E PROM Serial Data Output E PROM Output Disable E PROM Standby E PROM Command Input E PROM Data Input E PROM Address Input E PROM During Programming E PROM During Erasing E PROMProgra m, Erase Inhibit Pseudo READ SRAM
2 2 2 2 2 2 2 2 2
CE1S
CE2S * L * L * L * L * L * L * L * L * L H H H H H H H H H
WE OE RE#n WE#n L H
UB
LB
CLE
ALE
CE#n WP#n
DQ0~DQ7
DQ8~ DQ15 Hi-Z
Add
H * H * H * H * H * H * H * H * H * L L L L
*
*
L
L
L
*
DOUT
*
H
H
*
*
L
L
L
*
Hi-Z
Hi-Z
*
*
H
*
*
L
L
H
*
S
S
S
H
*
*
H
L
L
*
COMAND-IN
Hi-Z
*
H
*
*
L
L
L
*
DIN
Hi-Z
*
H
*
*
L
H
L
*
AIN
Hi-Z
*
H
H
*
*
*
*
*
H
N
Hi-Z
*
H
H
*
*
*
*
*
H
N
Hi-Z
*
H L L L H H H H L *
H H H H L L L H H *
* L H L L H L * H *
* L L H L L H * H *
* L L L L L L * * *
* L L L L L L * * *
* H H H H H H H H *
L * * * * * * * * *
N DOUT DOUT Hi-Z DIN DIN Hi-Z Hi-Z Hi-Z N
Hi-Z DOUT Hi-Z DOUT DIN Hi-Z DIN Hi-Z Hi-Z N
* ** ** ** ** ** ** ** ** *
Pseudo WRITE
SRAM
L L
Pseudo SRAM Output Disable Pseudo SRAM Standby Pseudo SRAM DeepPower-dow n Standby
L L H
H
L
*
*
*
*
*
*
*
*
N
N
*
Notes:*: **:
Don't Care At CE1S falling edge, all address(A2 to A20) are valid "IN". Page address signals(A0 and A1) must be VIH or VIL, during entire cycle. DIN: Data IN AIN: Address In DOUT: Data Out Hi-Z: High impedance COMAND-IN: Command Input 2 N: Depends on E PROM memory operation mode S: Depends on Pseudo SRAM operation Mode Does not apply when CE#n = CE1S = VIL and CE2S = VIH at the same time.
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ABSOLUTE MAXIMUM RATINGS
SYMBOL VCC VIN VDQ Topr PD Tsolder Ishort Tstg PARAMETER VCCs/VCCn Supply Voltage Input Voltage Input/Output Voltage Operating Temperature Power Dissipation Soldering Temperature (10 s) Output Short Circuit Current Storage Temperature RANGE -0.3~3.6 -0.3~3.6 -0.5~VCC + 0.3 ( 3.6) -25~85 0.6 260 100 -55~125 UNIT V V V C W C mA C
RECOMMENDED DC OPERATING CONDITIONS (Ta = -25~85C)
SYMBOL VCCs/VCCn,VCCqn, VIH VIL VDH PARAMETER Power Supply Voltage Input High-Level Voltage Input Low-Level Voltage Data Retention Voltage for Pseudo SRAM MIN 2.7 2.2 -0.3 2.5 TYP. MAX 3.1 VCC + 0.3 0.4 3.0 V UNIT
CAPACITANCE (Ta = 25C, f = 1 MHz)
SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance CONDITION VIN = GND VOUT = GND MIN TYP. MAX 15 20 UNIT pF pF
Note: These parameters are sampled periodically and are not tested for every device.
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DC CHARACTERISTICS (Ta = -25~85C, VCCs/VCCn = 2.7 V~3.1 V)
SYMBOL IIL ISOH ISOL IFOH IFOL IFOL ( RY/BY ) ILO ICCO1 ICCO2 PARAMETER Input Leakage Current Pseudo SRAM Output High Current Pseudo SRAM Output Low Current E PROM Output High Current (TTL) E PROM Output Low Current E PROM Output Current of RY/BY pin Output Leakage Current E PROM Operating Current (Serial Read) E PROM Operating Current (Command Input) E PROM Operating Current ICCO3 (Data Input) E PROM Operating Current (Address Input) E PROM Programming Current E PROM Erasing Current Pseudo SRAM Operating Current
2 2 2 2 2 2 2 2 2
CONDITION VIN = 0 V~VCC VOH = 2.0 V VOL = 0.4 V VOH = 2.4 V VOL = 0.4 V VOL = 0.4 V VOUT = 0 .4V~VCC, OE = VIH CE#n= VIL, IOUT = 0 mA, tcycle = 50ns tcycle = 50 ns
MIN -0.5 1.0 -0.4 2.1
TYP. MAX UNIT 8 10 10 10 30 A mA mA mA mA mA A mA
10
30
mA
tcycle = 50 ns
10
30
mA
ICCO4 ICCO5 ICCO6 ICCO7
tcycle = 50 ns CE2S = VIH, CE1S = Cycling IOUT = 0 mA, CE2S = VIH , CE1S = VIL , Page add. cycling, IOUT= 0 mA CE#n= VIH CE#n= VCCn- 0.2 V
CE1S = VIH, CE2S = VIH CE1S = VCCs - 0.2 V, CE2S = VCCS - 0.2 V
tRC = Min tRC = 1us tRC = Min
10 10 10
30 30 30 40 5 25 1 100 3 70 5
mA mA mA mA mA mA mA A mA A A
ICCO8 ICCS1 ICCS2 ICCS3 ICCS4 ICCS5
Pseudo SRAM Page Access Operating Current E PROM Standby Current(TTL) E PROM Standby Current(MOS) Pseudo SRAM Standby Current (TTL) Pseudo SRAM Standby Current(MOS) Pseudo SRAM Deep Power-down Standby Current
2 2
CE2S = 0.2 V
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AC CHARACTERISTICS AND OPERATING CONDITIONS(Pseudo SRAM)
(Ta = -25C~85C, VDD = 2.7~3.1 V)
SYMBOL tRC tCE tP tCEA tOEA tOEP tBEA tAPH tASC tAHC tASO, tASW tAHO, tAHW tWHC tRCS tRCH tWP tWCH tCWL tWBH tBWL tWR tDSW tDSC tDSB tDHW tDHC tDHB tCLZ tOLZ tBLZ tWLZ tCHZ tOHZ tBHZ tWHZ tPC tAA tAOH tCS tCH tDPD tCHC tCHP Read or Write Cycle Time
CE1S Pulse Width
PARAMETER
MIN 100 85 15 85 85 -15 70 0 70 0 10 10 85 85 85 50 85 0 30 30 30 0 0 0 10 0 0 0 25 10 0 200 10 0 30
MAX 10000 85 85 10000 25 10000 20 20 20 20 25
UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ms ns s
Pre-charge Time
CE1S Access Time OE Access Time OE Pulse Width
LB , UB Access Time Address(A0 and A1) Hold Time Address Set-up Time Address Hold Time Address Set-up Time Address Hold Time WE Hold Time Read Command Set-up Time Read Command Hold Time WE Pulse Width
CE1S to End of Write
Write Command to CE1S Lead Time LB , UB to End of Write Write Command to LB , UB Lead Time Write Recovery Time Data Set-up Time from WE Data Set-up Time from CE1S Data Set-up Time from LB , UB Data Hold Time from WE Data Hold Time from CE1S Data Hold Time from LB , UB
CE1S Low to Output Active OE Low to Output Active
LB , UB Low to Output Active WE Low to Output Active
CE1S High to Output High-Z OE High to Output High-Z
LB , UB High to Output High-Z
OE High to Output High-Z
Page Mode Cycle Time Page Mode Address Acess Time Page Mode Output Data Hold Time CE2S Set-up Time CE2S Hold Time CE2S Pulse Width(Deep Power Down) CE2S Hold from CE1S (Power On) CE2S Hold from Power On
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AC TEST CONDITIONS Pseudo SRAM
CONDITION VCCS- 0.2V, 0.2 V 5 ns VCCS x 0.5 VCCS x 0.5 CL (30 pF) + 1 TTL Gate
PARAMETER Input Pulse Level Input Pulse Rise and Fall Time (10%~90%) Timing Measurement Reference Level (input) Timing Measurement Reference Level (output) Output Load
AC TEST CONDITIONS
NAND E2PROM
CONDITION 0.4 V, 2.4 V 5 ns VCCn x 0.5 VCCn x 0.5 CL (30 pF) + 1 TTL Gate
PARAMETER Input Pulse Level Input Pulse Rise and Fall Time (10%~90%) Timing Measurement Reference Level (input) Timing Measurement Reference Level (output) Output Load
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AC CHARACTERISTICS AND OPERATING CONDITIONS(NAND E2PROM ) (Ta = -25C~85C, VDD = 2.7~3.1 V)
SYMBOL tCLS tCLH tCS tCH tWP tALS tALH tDS tDH tWC tWH tWW tRR tRP tRC tREA tCEA tREAID tOH tRHZ tCHZ tREH tIR tRSTO tCSTO tRHW tWHC tWHR tAR1 tCR tR tWB tAR2 tRST CLE Setup Time CLE Hold Time PARAMETER MIN 0 10 0 10 30 0 10 20 10 50 20 100 20 40 60 10 20 0 0 30 30 100 100 50 MAX 40 45 40 30 20 40 50 25 200 6/10/500 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns ns s NOTES
CE#n Setup Time CE#n Hold Time
Write Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time WE#n High Hold Time
WP High to WE#n Low
Ready to RE#n Falling Edge Read Pulse Width Read Cycle Time RE#n Access Time (Serial Data Access)
CE#n Access Time (Serial Data Access)
RE#n Access Time (ID Read) Data Output Hold Time RE#n High to Output High Impedance
CE#n High to Output High Impedance
RE#n High Hold Time Output-High-impedance-to- RE#n Rising Edge RE#n Access Time (Status Read)
CE#n Access Time (Status Read)
RE#n High to WE#n Low WE#n High to CE#n Low WE#n High to RE#n Low ALE Low to RE#n Low (ID Read)
CE#n Low to RE#n Low (ID Read)
Memory Cell Array to Starting Address WE#n High to Busy ALE Low to RE#n Low (Read Cycle) Device Reset Time (Read/Program/Erase)
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Note: (1) CE#n High to Ready time depends on the pull-up resistor tied to the RY/ BY pin. (Refer to Application Note (20) toward the end of this document.) (2) Sequential Read is terminated when tCEH is greater than or equal to 100 ns. If the RE#n to CE#n delay is less than 30 ns, RY/ BY signal stays Ready
. tCEH 100 ns * CE#n *: VIH or VIL
RE#n 525 526
527
A
A : 0 30 ns Busy signal is not output.
RY/BY Busy
PROGRAMMING AND ERASING CHARACTERISTICS (Ta = -25 to 85, VCC = 2.7 V to 3.1V)
SYMBOL tPROG N tBERASE PARAMETER Programming Time Number of Programming Cycles on Same Page Block Erasing Time MIN TYP. 200 3 MAX 1000 10 5 ms UNIT s (1) NOTES
(1): Refer to Application Note (23) toward the end of this document.
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TIMING DIAGRAMS
PSEUDO SRAM READ TIMING
tCE
CE1S
tP *
* tCH tRC
CE2S tASC A0~A1 tAHC A2~A20 tASO
OE
tAPH
tAHO
tP *
* tRCS
tRCH tOEP tOEA tBEA
WE
tCHZ
LB , UB tOLZ tBLZ DOUT tCLZ tCEA * In this section, either OE or CE1S is set to High. tBHZ Valid Data Out tOHZ
PSEUDO SRAM PAGE TIMING (4 words access)
tCE
CE1S
tP *
* tCH tRC
CE2S tAPH A0~A1 tASC A2~A20 tASO
OE
tPC
tPC
tPC
tAHC
tAHO
tP *
* tRCS tRCH tOEA tBEA tOLZ
WE
LB , UB tBLZ DOUT tCLZ tCEA * Dout tAA tAOH Dout tAA tAOH Dout tAA tAOH Dout tCZH
In this section, either OE or CE1S is set to High.
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PSEUDO SRAM WRITE TIMING ( WE Control Write)
tCE
CE1S
tP
tCH CE2S tASC A0~A1 tASW A2~A20 tAHW
tRC tWR tAPH
tCWL tWP WE tWHC tWCH LB , UB tWBH DIN tDSW DOUT Hi-Z Valid Data In tDHW
tP
PSEUDO SRAM WRITE TIMING (LB / UB Control Write)
tCE
CE1S
tP
tCH CE2S tASC A0~A1 tASW A2~A20 tWCH tAHW
tRC tWR tAPH
tP tWP
WE tWHC tWBL LB , UB tWBH DIN tDSB DOUT Hi-Z Valid Data In tDHB tCWL
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PSEUDO SRAM WRITE TIMING (CE1S Control Write)
tCE
CE1S
tP
tCH CE2S tASC A0~A1 tASW A2~A20 tWHC WE tAHW tAHC tAPH
tRC tWR
tCWL
tBWL LB , UB tDSC DIN tCLZ DOUT tWHZ Hi-Z Valid Data In tDHC
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POWER ON TIMING
VCCS
VCCS min
CE1S
tCS
tCHC
CE2S tCHP
tCH
PSEUDO SRAM DEEP POWER-DOWN TIMING
CE1S
tDPD CE2S tCS tCH
PSEUDO SRAM PROHIBITION TIMING
CE1S
CE2S
OE
WE
The timing shown above is prohibited. If both OE and WE go Low coincident with or before falling edge of CE1S , a malfunction may occur since devices go into test modes for internal use.
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APPLICATION NOTES AND COMMENTS
Note: (1) (2) (3) (4) (5) (6) (7) (8) Stresses greater than listed under "Absolute Maximum Ratings" may cause permanent damage to the device. All voltages are reference to GND. ICCO depends on the cycle time. ICCO depends on output loading. Specified values are defined with the output open condition. After power-up, an initial pause of 200 s with CE2S high is required with the output open condition. AC measurements are assumed tT = 5 ns. Parameters tCHZ, tOHZ, tBHZ and tWHZ define the time at which the output goes the open condition and are not output voltage reference levels. During write cycles, input data is latched on the earliest of WE , LB / UB or CE1S rising edge. Therefore, input data must be valid during the set-up time (tDSC, tDSB or tDSW) and hold time(tDHC, tDHB or tDHW). Address(A2 to A20) inputs are latched on the falling edge of CE1S . Therefore, addresses(A2 to A20) input must be valid during the set-up time (tASC) and hold time(tAHC). Data cannot be retained at deep power-down stand-by mode If OE is high during the write cycle, the outputs will remain at high impedance. During the output state of DQ signals, input signals of reverse polarity must not be applied.
(9) (10) (11) (12)
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Latch Timing Diagram for Command/Address/Data
CLE ALE CE#n RE#n
Setup Time
Hold Time
WE#n tDS DQ0 to DQ7 tDH
: VIH or VIL
Command Input Cycle Timing Diagram
CLE
tCLS tCS
tCLH tCH
CE#n tWP
WE#n tALS tALH
ALE tDS DQ0 ~DQ7 tDH
Command
: VIH
or VIL
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Address Input Cycle Timing Diagram
tCLS
CLE tCS tWC tWC tCH CE#n tWP tWH tWP tWH tWP tCS tCH
WE#n tALS tALH
ALE tDS DQ0 ~DQ7 tDH tDS tDH tDS tDH
A0~A7
A9~A16
A17~A22
: VIH or VIL
Data Input Cycle Timing Diagram
tCLH
CLE tCH tCH CE#n tALS tWC tCS
ALE tWP tWH tWP tWP
WE#n tDS DQ0 ~DQ7 tDH tDS tDH tDS tDH
DIN0
DIN1
DIN 527
: VIH or VIL
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Serial Read Cycle Timing Diagram
tRC
CE#n tRP RE#n tREA DQ0 ~DQ7 tRR tOH tRHZ tREA tOH tRHZ tREA tOH tRHZ tREH tRP tCH tRP tCHZ
tCEA
RY/BY : VIH or VIL
Status Read Cycle Timing Diagram
tCLS
CLE
tCLS tCS
tCLH
CE#n tWP tCH
WE#n
tWHC tWHR
tCSTO
tCHZ
RE#n tDS DQ0 ~DQ7 tDH tIR tRSTO tOH tRHZ
70H*
Status output
RY/BY
* 70H represents the hexadecimal number
: VIH or VIL
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Read Cycle (1) Timing Diagram
CLE
tCLS tCS
tCLH tCH
CE#n tWC
WE#n tALH tALS tALH tAR2
ALE tr tWB tDS tDH DQ0 ~DQ7 tDS tDH tDS tDH tDS tDH tREA DOUT N DOUT N+1 DOUT N+2 DOUT 527 tRR tRC
RE#n
00H
A0~A7 Column address N*
A9~A16
A17~A22
RY / BY : VIH or VIL
Read Cycle (1) Timing Diagram: When Interrupted by CE#n
CLE
tCLS tCS
tCLH tCH
CE#n
t
WE#n tALH tALS
tCHZ
t
tr tWB
tAR2
ALE tRR tRC
RE#n tDS tDH DQ0 ~DQ7 tDS tDH tDS tDH tDH tREA DOUT N DOUT N+1
tOH tRHZ DOUT N+2
00H
A0~A7 Column address N*
A9~A16
A17~A22
RY/BY * Read Operation using 00H Command N: 0 to 255 : VIH or VIL
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Read Cycle (2) Timing Diagram
CLE
tCLS tCS
tCLH tCH
CE#n
WE#n tALH tALS tALH tAR2
ALE
tr tWB tDS tDH tDS tDH
tRR
tRC
RE#n
tREA
DQ0 ~DQ7
01H
A0~A7 A9~A16 A17~A22 Column address N*
DOUT
DOUT
DOUT 527
256 + N 256 + N + 1
RY / BY *: Read Operation using 01H Command N: 0 to 255 : VIH or VIL
Read Cycle (3) Timing Diagram
CLE
tCLS tCS
tCLH tCH
CE#n
WE#n tALH tALS tALH tAR2
ALE tr tWB tDS tDH DQ0 ~DQ7 tDS tDH tREA tRR tRC
RE#n
50H
A9~A16 A17~A22 Column address N*
DOUT
DOUT
DOUT 527
512 + M 512 + M + 1
RY / BY : VIH or VIL *: Read Operation using 50H Command N: 0 to15
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Sequential Read (1) Timing Diagram
CLE
CE#n
WE#n
ALE
RE#n
DQ0 ~DQ7
00H
A0~A7 A9~A16 A17~A22 Column address N Page address M tr
N
N+1 N+2
527 tr
0
1
2
527
RY/BY Page M access Page M + 1 access : VIH or VIL
Sequential Read (2) Timing Diagram
CLE
CE#n
WE#n
ALE
RE#n
DQ0 ~DQ7
01H
A0 to A7 A9~A16 A17~A22 Page Column address address M N tr 256 + 256 + 256 + N N+1 N+2
527 tr
0
1
2
527
RY/BY Page M access Page M + 1 access : VIH or VIL
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Auto-Program Operation Timing Diagram
tCLS CLE
tCLS
tCLH tCS
CE#n tCS WE#n tCH
tALH tALS
tALH tALS
tPROG tWB
ALE
RE#n tDS tDH DQ0 ~DQ7 80H tDS tDH A0~A7 A9~A16 A17~A22
tDS tDH DIN0 DIN1 DIN 527 10H tDS t DH 70H Status output
RY/BY : VIH or VIL : Do not input data while data is being output.
Auto Block Erase Timing Diagram
CLE
tCLS tCS tCLH tCLS
CE#n
WE#n tALS ALE tALH tWB tBERASE
RE#n tDS tDH DQ0 ~DQ7 60H A9~A16 A17~A22 D0H 70H Status output RY/BY Auto Block Erase Setup command Erase Start command : VIH or VIL Busy Status Read command
Do not input data while data is being output.
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ID Read Operation Timing Diagram
CLE
t
tCS CE#n tCH
tCLS tCS
tCH
WE#n tALH tALS tALH
tCR tAR1
ALE
RE#n tDS DQ0 ~DQ7 tDH tREAID tREAID
90H
00
98H
E6H
Address input
Maker code
Device code
: VIH or VIL
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NAND PIN FUNCTIONS
Command Latch Enable: CLE
The CLE input signal is used to control loading of the operation mode command into the internal command register. The command is latched into the command register from the DQ port on the rising edge of the WE#n signal while CLE is High.
Address Latch Enable: ALE
The ALE signal is used to control loading of either address information or input data into the internal address/data register. Address information is latched on the rising edge of WE#n if ALE is High. Input data is latched if ALE is Low.
Chip Enable: CE#n
The device goes into a low-power Standby mode when CE#n goes High during a wait state. The CE#n signal is ignored when device is in Busy state (R/B= L), such as during a Program or Erase or Read operation, and will not enter Standby mode even if the CE#n input goes High..
Write Enable: WE#n
The WE#n signal is used to control the acquisition of data from the DQ port.
Read Enable: RE#n
The RE#n signal controls serial data output. Data is available tREA after the falling edge of RE#n. The internal column address counter is also incremented (Address = Address + l) on this falling edge.
DQ Port: DQ0 to 7
The DQ0 to 7 pins are used as a port for transferring address, command and input/output data to and from the device.
Write Protect: WP#n
The WP#n signal is used to protect the device from accidental programming or erasing. The internal voltage regulator is reset when WP#n is Low. This signal is usually used for protecting the data during the power-on/off sequence when input signals are invalid.
Ready/Busy: RY/BY
The RY/BY output signal is used to indicate the operating condition of the device. The RY/BY signal is in Busy state ( RY/BY = L) during the Program, Erase and Read operations and will return to Ready state ( RY/BY = H) after completion of the operation. The output buffer for this signal is an open drain.
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Schematic Cell Layout and Address Assignment
The Program operation works on page units while the Erase operation works on block units.
DQ0 512 16 DQ7
A page consists of 528 bytes in which 512 bytes are used for main memory storage and 16 bytes are for redundancy or for other uses. 1 page = 528 bytes 1 block = 528 bytes x 16 pages = (8K + 256) bytes Capacity = 528 bytes x 16 pages x 1024 blocks An address is read in via the DQ port over three consecutive clock cycles, as shown in Table 1.
16384 pages 1024 blocks = 8DQ 528 Figure 2. Schematic Cell Layout Table 1. Addressing DQ7 First cycle Second cycle Third cycle A7 A16 *L DQ6 A6 A15 *L DQ5 A5 A14 A22 *: Table 2. Logic table Command Input Data Input Address Input Serial Data Output During Read (Busy) During Programming (Busy) During Erasing (Busy) Program, Erase Inhibit H: VIH, L: VIL, *: VIH or VIL
16 pages 1 block = DQ4 A4 A13 A21 DQ3 A3 A12 A20
DQ2 A2 A11 A19
DQ1 A1 A10 A18
DQ0 A0 A9 A17 A0~A7: A9~A22: A13~A22: A9~A12: Column address Page address Block address NAND address in block
A8 is automatically set to Low or High by a 00H command or a 01H command. DQ6 and DQ7 must be set to Low in the third cycle .
Operation Mode: Logic and Command Tables
The operation modes such as Program, Erase, Read and Reset are controlled by the ten different command operations shown in Table 3. Address input, command input and data input/output are controlled by the CLE, ALE, CE#n, WE#n, RE#n, WP#n and signals, as shown in Table 2.
CLE H L L L * * * * *
ALE L L H L * * * * *
CE#n L L L L L H * * *
WE#n
RE#n H H H
WP#n * * * *
H H * * * * H * * * *
* * H H L
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Table 3. Command table (HEX) First Cycle Serial Data Input Read Mode (1) Read Mode (2) Read Mode (3) Reset Auto Program Auto Block Erase Status Read ID Read 80 00 01 50 FF 10 60 70 90 Second Cycle D0 1 0 0 5 0 4 0 3 0 2 0 0 Acceptable while Busy HEX data bit assignment (Example) Serial data input: 80H
DQ7 6
1 DQ0
Table 4 shows the operation states for Read mode.
Table 4. Read mode operation states CLE Output Select Output Deselect H: VIH, L: VIL L L ALE L L CE#n L L WE#n H H RE#n L H DQ0~DQ7 Data output High impedance Power Active Active
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NAND DEVICE OPERATION
Read Mode (1)
Read mode (1) is set when a 00H command is issued to the Command register. Refer to Figure 3 below for timing details and the block diagram.
CLE CE#n WE#n ALE RE#n RY/BY M DQ 00H Start-address input M 527 A data transfer operation from the cell array to the register starts on the rising edge of WE#n in the third cycle (after the address information has been latched). The device will be in Busy state during this transfer period. After the transfer period the device returns to Ready state. Serial data can be output synchronously with the RE#n clock from the start pointer designated in the address input cycle. Busy
N
Select page N Figure 3. Read mode (1) operation
Cell array
Read Mode (2)
CLE CE#n WE#n ALE RE#n
RY/BY
M DQ 01H
N
Busy
Start-address input 256 M 527 The operation of the device after input of the 01H command is the same as that of Read mode (1). If the start pointer is to be set after column address 256, use Read mode (2). Cell array Figure 4. Read mode (2) operation
Select page N
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Read Mode (3)
Read mode (3) has the same timing as Read modes (1) and (2) but is used to access information in the extra 16-byte redundancy area of the page. The start pointer is therefore set to a value between byte 512 and byte 527.
CLE CE#n WE#n ALE RE#n
RY/BY
DQ 50H A0~A3 512 527
Busy
Addresses bits A0~A3 are used to set the start pointer for the redundant memory cells, while A4~A7 are ignored. Once a 50H command has been issued, the pointer moves to the redundant cell locations and only those 16 cells can be addressed, regardless of the value of the A4-to-A7 address. (An 00H command is necessary to move the pointer back to the 0-to-511 main memory cell location.)
Figure 5. Read mode (3) operation
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Status Read
The device automatically implements the execution and verification of the Program and Erase operations. The Status Read function is used to monitor the Ready/Busy status of the device, determine the result (pass/fail) of a Program or Erase operation, and determine whether the device is in Protect mode. The device status is output via the DQ port on the RE#n clock after a 70H command input. The resulting information is outlined in Table 5.
Table 5. Status output table STATUS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Pass/Fail Not Used Not Used Not Used Not Used Not Used Ready/Busy Write Protect Pass: 0 0 0 0 0 0 Ready: 1 Protect: 0 Busy: 0 Not Protected: 1 The Pass/Fail status on DQ0 is only valid when the device is in the Ready state. OUTPUT Fail: 1
An application example with multiple devices is shown in Figure 6.
CE#N1 CLE ALE WE#n RE#n DQ0~DQ7 CE#N2 CE#N3 CE#Nn CE#Nn+1
Device 1
Device 2
Device 3
Device n
Device n+1
RY/BY RY/BY
CLE ALE WE#n CE#N1 CE#Nn RE#n Busy
DQ
70H Status on Device 1
70H Status on Device N
Figure 6. Status Read timing application example
System Design Note: If the RY/BY pin signals from multiple devices are wired together as shown in the diagram, the Status Read function can be used to determine the status of each individual device.
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Auto Page Program
The device carries out an Automatic Page Program operation when it receives a "10H" Program command after the address and data have been input. The sequence of command, address and data input is shown below. (Refer to the detailed timing chart.)
Pass
80
10
70 Status Read command
DQ
Data input Address Data input Program command input 0 to 527 command
Fail
RY/BY
R/B automatically returns to Ready after completion of the operation. Program Reading & verification The data is transferred (programmed) from the register to the selected page on the rising edge of WE#n following input of the "10H" command. After programming, the programmed data is transferred back to the register to be automatically verified by the device. If the programming does not succeed, the Program/Verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached.
Data input
Selected page
Figure 7. Auto Page Program operation
Auto Block Erase
The Auto Block Erase operation starts on the rising edge of WE#n after the Erase Start command "D0H" which follows the Erase Setup command "60H". This two-cycle process for Erase operations acts as an ertra layer of protection from aceidental erasure of data due to external noise. The device automatically executes the Erase and Verify operations.
Pass
60 Block Address input: 2 cycles
D0 Erase Start Busy
70 Status Read command
DQ
Fail
RY/BY
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Reset
The Reset mode stops all operations. For example, in the case of a Program or Erase operation the internally generated voltage is discharged to 0 volts and the device enters Wait state. The response to an "FFH" Reset command input during the various device operations is as follows:
When a Reset (FFH) command is input during programming
Figure 8. 80 10 FF 00
Internal VPP
RY/BY
tRST (max 10 s)
When a Reset (FFH) command is input during erasing
Figure 9. D0 Internal erase voltage FF 00
RY/BY
tRST (max 500 s)
When a Reset (FFH) command is input during Read operation
Figure 10. 00 FF 00
RY/BY
tRST (max 6 s)
When a Status Read command (70H) is input after a Reset
Figure 11. FF 70 DQ status: Pass/Fail Pass Ready/Busy Ready
RY/BY
FF
70 DQ status: Ready/Busy Busy
RY/BY
When two or more Reset commands are input in succession
Figure 12. (1) FF (2) FF (3) FF
RY/BY
The second FF command is invalid, but the third FF command is
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ID Read
The TH50VPN5640EBSB contains ID codes which identify the device type and the manufacturer. The ID codes can be read out under the following timing conditions:
CLE tCR CE#n WE#n tAR1 ALE
RE#n tREAID DQ 90H ID Read command 00 Address 00 98H Maker code 73H Device code
For the specifications of the access times tREAID, tCR and tAR1 refer to the AC Characteristics. Figure 13. ID Read timing
Table 6. ID Codes read out by ID read command 90H
DQ7 Maker code Device code 1 1 DQ6 0 1 DQ5 0 1 DQ4 1 0 DQ3 1 0 DQ2 0 1 DQ1 0 1 DQ0 0 0 Hex Data 98H E6H
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APPLICATION NOTES AND COMMENTS
(13) Power-on/off sequence: The WP#n signal is useful for protecting against data corruption at power-on/off. The following timing sequence is necessary. The WP#n signal may be negated any time after the VCC reaches 2.5 V and CE#n signal is kept high in power up sequence.
2.7 V 2.5 V 0V CE#n, WE#n, RE#n CLE, ALE VIL Operation Figure 15. Power-on/off Sequence VCC Don't care VIH VIL Don't care
WP#n
In order to operate this device stably, after VCC becomes 2.5 V, it recommends starting access after about 200 s.
(14) Status after power-on The following sequence is necessary because some input signals may not be stable at power-on.
Power on
FF Reset Figure
(15) Prohibition of unspecified commands The operation commands are listed in Table 3. Input of a command other than those specified in Table 3 is prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle. (16) Restriction of command while Busy state During Busy state, do not input any command except 70H and FFH. (17) Acceptable commands after Serial Input command "80H" Once the Serial Input command "80H" has been input, do not input any command other than the Program Execution command "10H" or the Reset command "FFH". If a command other than "10H" or "FFH" is input, the Program operation is not performed.
80 XX 10 For this operation the "FFH" command is Command other than "10H" or "FFH" Programming cannot be
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(18) Status Read during a Read operation
00 command CE#n WE#n RY/BY RE#n Address N 00 70 [A]
Status Read command input Figure 18.
Status Read
Status output
The device status can be read out by inputting the Status Read command "70H" in Read mode. Once the device has been set to Status Read mode by a "70H" command, the device will not return to Read mode. Therefore, a Status Read during a Read operation is prohibited. However, when the Read command "00H" is input during [A], Status mode is reset and the device returns to Read mode. In this case, data output starts automatically from address N and address input is unnecessary
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(19) Pointer control for "00H", "01H" and "50H" The device has three Read modes which set the destination of the pointer. Table 7 shows the destination of the pointer, and Figure 14 is a block diagram of their operations.
Table 8. Pointer Destination Read Mode (1) (2) (3) Command 00H 01H 50H Pointer 0 to 255 256 to 511 512 to 527 (1) 00H (2) 01H (3) 50H 0 A 255 256 B 511 512 527 C
Pointer control Figure 19. Pointer control
The pointer is set to region A by the "00H" command, to region B by the "01H" command, and to region C by the "50H" command. (Example) The "00H" command must be input to set the pointer back to region A when the pointer is pointing to region C.
00H Add Start point A area Add Start point A area 00H Add Start point C area Add Start point C area Add Start point A area 50H Add Start point C area
50H
01H Add Start point B area Add Start point A area
To program region C only, set the start point to region C using the 50H command.
50H
80H Add DIN Start point C Area
10H Programming region C only
01H
80H Add DIN Start point B Area
10H Programming region B and C
Figure 20. Example of How to Set the Pointer
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(20) RY/ BY : termination for the Ready/Busy pin ( RY/ BY ) A pull-up resistor needs to be used for termination because the RY/ BY buffer consists of an open drain circuit.
VCCn VCCn Device CL VSS Figure 21. tr This data may vary from device to device. We recommend that you use this data as a reference when selecting a resistor value. 1.5 s 1.0 s 0.5 s 0 1 K tr 5 ns tf Ready 3.0 V RY/BY tf VCCn 1.0 V Busy 1.0 V tr VCCn = 3.3 V Ta = 25C CL = 100 pF 3.0 V
R
15 ns 10 ns tf
2 K R
3 K
4 K
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(21) Note regarding the WP#n signal The Erase and Program operations are automatically reset when WP#n goes Low. The operations are enabled and disabled as follows:
Enable Programming
WE#n
DIN WP#n
80
10
RY/BY tWW (100 ns min) Disable Programming
WE#n DIN WP#n 80 10
RY/BY tWW (100 ns min)
Enable Erasing
WE#n DIN 60 D0
WP#n RY/BY tWW (100 ns min) Disable Erasing
WE#n
DIN WP#n
60
D0
RY/BY tWW (100 ns min)
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(22) When four address cycles are input Although the device may read in a fourth address, it is ignored inside the chip.
Read operation
CLE
CE#n
WE#n
ALE
DQ 00H, 01H, 50H RY/BY Internal read operation starts when WE#n goes High in the third cycle. Figure 22. Program operation Address input Ignored
CLE
CE#n
WE#n
ALE
DQ
80H Address input Ignored Figure 23. Data input
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(23) Several programming cycles on the same page (Partial Page Program) A page can be divided into up to 10 segments. Each segment can be programmed individually as follows:
1st programming
Data Pattern 1
All 1s
2nd programming
All 1s
Data Pattern 2
All 1s
3rd programming
All 1s
Data Pattern 3
All 1s
Result
Data Pattern 1
All 1s
Data Pattern 2
All 1s
Data Pattern 3
All 1s
Figure 24. Note: The input data for unprogrammed or previously programmed page segments must be "1" (i.e. the inputs for all page bytes outside the segment which is to be programmed should be set to all "1").
(24)
Note regarding the RE#n signal RE#n The internal column address counter is incremented synchronously with the RE#n clock in Read mode. Therefore, once the device has been set to Read mode by a "00H", "01H" or "50H" command, the internal column address counter is incremented by the RE#n clock independently of the address input timing, If the RE#n clock input pulses start before the address input, and the pointer reaches the last column address, an internal read operation (array to register) will occur and the device will enter Busy state. (Refer to Figure 25.)
Hence the RE#n clock input must start after the address input.
DQ 00H/01H/50H
Address input
WE#n
RE#n
RY/BY Figure 25.
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(25) Invalid blocks (bad blocks) The device contains unusable blocks. Therefore, at the time of use, please check whether a block is bad and do not use these bad blocks. At the time of shipment, all data bytes in a Valid Block are FFH. For Bad Block, all bytes are not in the FFH state. Please don't perform erase operation to Bad Block. Check if the device has any bad blocks after installation into the system. Figure 27 shows the test flow for bad block detection. Bad blocks which are detected by the test flow must be managed as unusable blocks by the system. A bad block does not affect the performance of good blocks because it is isolated from the Bit line by the Select gate
Bad Block
Bad Block
Figure 26.
The number of valid blocks at the time of shipment is as follows:
MIN Valid (Good) Block Number 1014 TYP. MAX 1024 UNIT Block
Bad Block Test Flow
Start
Read Check: to verify all pages in the block with FF (Hex)
Block No = 1
Fail Read Check Pass Block No. = Block No. + 1 Bad Block *1
No Block No. = 1024 Yes End
*1: No erase operation is allowed to detected bad blocks
Figure 27
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(26) Failure phenomena for Program and Erase operations The device may fail during a Program or Erase operation. The following possible failure modes should be considered when implementing a highly reliable system.
FAILURE MODE Block Page Erase Failure Programming Failure Programming Failure 10
DETECTION AND COUNTERMEASURE SEQUENCE Status Read after Erase Block Replacement Status Read after Program Block Replacement (1) Block Verify after Program Retry (2) ECC
Single Bit
* *
ECC: Error Correction Code Block Replacement
Program
Error occurs Buffer memory
Block A
When an error happens in Block A, try to reprogram the data into another Block (Block B) by loading from an external buffer. Then, prevent further system accesses to Block A (by creating a bad block table or by using an another appropriate scheme).
Block B
Figure 28. Erase
When an error occurs in an Erase operation, prevent future accesses to this bad block (again by creating a table within the system or by using another appropriate scheme).
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PACKAGE DIMENSIONS
Unit: mm
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